1. Field of the Invention
The invention relates in general to the fabrication of metal-oxide-semiconductor (MOS) transistors, and more particularly to the fabrication of dual voltage MOS transistors.
2. Description of the Related Art
It is nowadays a tendency to have dual operation voltage for some applications in deep sub-micron regime where the operation voltage of a core device is less than that of a I/O device due to the scaling down of channel length. However, the main obstacle is that the device performance of high and low voltage can not be satisfied simultaneously in current process.
FIG. 1A to FIG. 1E illustrate conventional processes of fabricating a dual voltage NMOS transistor. Referring first to FIG. 1A, the starting material is a lightly doped (.about.5E14 to 1E16 atoms/cm.sup.3) &lt;100&gt; silicon substrate 100. Then, active regions and field regions are desired to be defined. This can be done by selectively oxidizing the field regions 102 so that they are covered with a thick field oxide, using the LOCOS process. Alternatively, shallow trench isolation technique can be applied to define the active regions. The n-well can be fabricated by implanting a n-type dopant into the p-substrate 100, using a photoresist mask (not shown) covering the p-substrate 100 but exposing the predetermined n-well region, and then performing ion implantation.
Referring to FIG. 1B, a first gate oxide layer is grown over the substrate 100. The first gate oxide is then partially etched, usually by HF wet etching, leaving only on the top surface of the substrate 100 desired for a high voltage NMOS (HV NMOS). The HF wet etching process usually causes the damage of oxide in the trenches. This leaving first gate oxide layer is numbered as 104a. Next, another gate oxide formation process is performed to grow an overlaying gate oxide 106, covering the first gate oxide 104a and the exposed top surface of the substrate 100 for the low voltage NMOS (LV NMOS). Therefore, the gate oxide for the HV NMOS is the combination of the first gate oxide layer 104a and the overlaying gate oxide layer 106 and is thus thicker than the gate oxide for the LV NMOS.
Referring to FIG. 1C, a layer of polysilicon of about 0.1.about.0.3 .mu.m thick, is next deposited by chemical vapor deposition (CVD) over the whole substrate 100. The main technique used to deposit polysilicon is low pressure chemical vapor deposition (LPCVD) because of its uniformity, purity, and economy. The gate structure is then patterned. Following exposure and development of the resist, the polysilicon film is dry-etched, using a photoresist mask (not shown)for protecting the desired regions for forming gates, to form a gate 108 for HV NMOS and another gate 110 for LV NMOS. The gate length of the gate 108 for HV NMOS is usually constructed wider than that of the gate 110 for LV NMOS.
Due to the continuous scaling of channel length, serious hot-carrier effects will cause unacceptable performance degradation. To overcome this problem, an alternative drain structures, lightly doped drains (LDD) is used. Since only NMOS is illustrated in FIG. 1D, only the fabricating processes of NMOS LDD structure are described. Referring to FIG. 1D, to form the NMOS LDD structure, a photoresist mask (not shown) covering the PMOS is first formed. The drains of both the HV NMOS and LV NMOS are then formed at least by two implants. One of these is self-aligned to the gate electrode, and the other is self-aligned to the gate electrode on which two sidewall spacers have been formed.
Referring to FIG. 1D, a first ion implantation process is performed, self-aligned to the gate electrodes 108, 110, penetrating the overlaying gate oxide layer 106 and the first gate oxide layer 104a to form lightly doped sections 112, 114 for both HV NMOS and LV NMOS, respectively. In NMOS devices, the preferred dose is about 1.about.5E14 atoms/cm.sup.2 of phosphorus or arsenic.
Referring to FIG. 1E, a gate sidewall spacer 120 having a thickness of about 0.08.about.0.10 .mu.m, is formed. The processes of forming the spacer 120 include: first, depositing a dielectric layer over the substrate 100 and etching back. Then, a heavier dose of dopant is implanted to form low resistivity regions 122 of the drain regions of both the HV NMOS and LV NMOS, which are also merged with the lightly doped region. For NMOS devices, this implant is arsenic or phosphorous at a dose of about 1E15 atoms/cm.sup.2.